Research & insights
Interactive: click any card for detail, read the papers in-app, and click a process module to open its cost bridge.
Pick a generation; click a module to open its cost bridge.
Real analyst estimates the model is calibrated to. Click a card for detail.
Front end
Wafer cost rises ~6.5× from 28 → 3 nm
28 nm ~$3,000 · 3 nm ~$19,500 · fixed cost +~15×
Back end
Packaging spans three orders of magnitude
wire-bond cents → CoWoS $300–2,000
How the industry bends the cost curve — each lever with research literature. Click to open.
Technology
Chiplet disaggregation
Split one large die into smaller, higher-yield chiplets; reuse and mix nodes. The most-studied fab-cost lever — cost superiority over monolithic SoC comes from yield improvement, chiplet/package reuse, and heterogeneity.
6 Papers →
Practice
Yield learning (ML)
Yield is the largest variable-cost driver. ML on wafer-map and inspection data cuts scrap and shortens ramp.
5 Papers →
Virtual metrology & APC
Predict wafer measurements from tool sensors, skip physical metrology steps and catch excursions early — directly reducing metrology cost and scrap.
2 Papers →
Predictive maintenance (OEE)
Tool downtime spreads fixed cost over fewer wafers. Predict unscheduled failures and schedule maintenance — ML beats human-judgment benchmarks.
1 Papers →
Test & assembly verification
Test is ~5–15% of cost. Front-end: adaptive / spatial-sampling test skips redundant coverage while holding accuracy. Back-end: built-in self-test and on-die impedance sensing verify chiplet/interposer assemblies without costly external testers.
3 Papers →
Fab energy & throughput
Simulate the whole line to raise throughput and cut energy (opex). Optimal scheduling cut energy per wafer by ~27% vs FIFO in one study.
Graphene photonics (FabONE)
The FabONE technology track. Graphene integrated at back-end-of-line onto finished CMOS chips turns electrical signals into light for chip-to-chip optical interconnects — CMOS-compatible, wafer-scale broadband modulators and detectors. This is the device physics behind the entitlement story: the papers below are the performance ceiling; the fab is what closes the manufacturing gap to it. "A reference fab for a technology that has no reference fab."
10 Papers →
Curated papers, rendered in-app. Click a card for the abstract and full text.
arXiv:2203.12268 · 2022
Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
Yinxiao Feng et al.
arXiv:2410.09188 · 2024
MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
Lukas Pfromm et al.
arXiv:2301.08974 · 2023
Soft Sensing Regression Model: from Sensor to Wafer Metrology Forecasting
Angzhi Fan et al.
arXiv:1904.07686 · 2019
Predicting Time-to-Failure of Plasma Etching Equipment using Machine Learning
Anahid Jalali et al.
arXiv:2506.03556 · 2025
Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning
Wang WeiQuan et al.
arXiv:2311.04947 · 2023
Global virtual factory simulation for energy efficiency
Jenil Agrawal et al.
arXiv:2411.04410 · 2024
The Survey of Chiplet-based Integrated Architecture: An EDA perspective
Shixin Chen et al.
arXiv:2306.07241 · 2023
An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects
V. S. P. Karempudi et al.
arXiv:2509.18355 · 2025
Chiplet-Based RISC-V SoC with Modular AI Acceleration
S. S. Bharadwaj et al.
arXiv:2407.20268 · 2024
GANs for Image Augmentation & Classification of Wafer Dicing-Induced Defects
Zhining Hu et al.
arXiv:2308.12299 · 2023
Inverse Lithography Physics-informed Deep Neural Level Set for Mask Optimization
Xing-Yu Ma et al.
arXiv:2606.00923 · 2026
Graph Attention-Based Virtual Metrology for Film Deposition Processes
Tao Han et al.
arXiv:2503.14784 · 2025
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging
Partho Bhoumik et al.
arXiv:2504.19418 · 2025
ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification
Saleh Khalaj Monfared et al.
arXiv:2206.07308 · 2022
Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies
Tianqi Tang et al.
arXiv:2507.20357 · 2025
Wafer Defect Root Cause Analysis with Partial Trajectory Regression
Kohei Miyaguchi et al.
arXiv:2512.11977 · 2025
A Comparative Analysis of Semiconductor Wafer Map Defect Detection with Image Transformer
Sushmita Nath et al.
arXiv:2309.17343 · 2023
Neural Lithography: Closing the Design-to-Manufacturing Gap with a Learned Photolithography Simulator
Cheng Zheng et al.
arXiv:1906.00353 · 2019
Graphene-Based Integrated Photonics for Next-Generation Datacom and Telecom
M. Romagnoli et al.
arXiv:2304.02646 · 2023
Wafer-scale Graphene Electro-absorption Modulators Fabricated in a 300mm CMOS Platform
Chenghan Wu et al.
arXiv:2506.03281 · 2025
Graphene Electro-Absorption Modulators for Energy-Efficient and High-Speed Optical Transceivers
M. Tiberi et al.
arXiv:1402.7127 · 2014
Multifunctional Graphene Optical Modulator and Photodetector Integrated on Silicon Waveguides
Nathan Youngblood et al.
arXiv:1804.10016 · 2018
Record High Bandwidth Integrated Graphene Photodetectors for Communication Beyond 180 Gb/s
Daniel Schall et al.
arXiv:2205.07051 · 2022
High-speed Graphene-Silicon-Graphene Waveguide Photodetectors with High Photo-to-Dark-Current Ratio
Jingshu Guo et al.
arXiv:2411.02269 · 2024
High-Speed Graphene-based Sub-Terahertz Receivers enabling Wireless Communications for 6G and Beyond
K. P. Soundarapandian et al.
arXiv:1009.4465 · 2010
Graphene Photodetectors for High-Speed Optical Communications
Thomas Mueller et al.
arXiv:2007.03044 · 2020
High-Responsivity Graphene Photodetectors Integrated on Silicon Microring Resonators
Simone Schuler et al.
arXiv:2203.05752 · 2022
Ultrafast Intrinsic Optical-to-Electrical Conversion Dynamics in a Graphene Photodetector
Katsumasa Yoshioka et al.