Reference Plant
Methodology
Every number here is synthetic and calibrated to public sources. This page is written to be audited: the model, the distributions, and the citations.
The Reference Fab methodology
Reference Plant is built on the Reference Fab methodology introduced at Infineon Technologies by Plieninger, Müller, Ehm and Reczek (IEEE/SEMI ASMC 2001). The original method sets cost targets top-down across three levels:
- ① Ideal Reference Fab — a greenfield fab at best-in-class performance in every cost category (capital, material, personnel, overhead), at high reference volume on a single reference product and technology.
- ③ Site-specific Reference Fab — the best-in-class target for a real site, obtained by applying factor/adders to the ideal fab for local conditions: factor costs, volume, technology complexity and outsourcing.
- ④ Catch-up plan — the transition of the actual site to its site-specific target, tracked monthly against the plan.
Cost is split into capital, material, personnel and overhead (~15 categories), each carrying an efficiency = factor input ÷ pieces out. Infineon's Memory Products Division cut production cost by more than 25% (25–50% efficiency gains) versus initial plans.
This demonstration: isolates the same idea — how well a plant is run, separated from where it sits — by re-pricing each process at one common reference (the site-specific normalization), then attributing the gap to six levers. The figures here are synthetic; the method is the paper's.
Source: R. Plieninger, U. Müller, H. Ehm & W. Reczek, “Cost Reduction using Systematic Target Setting of the Reference Fab Methodology,” 2001 IEEE/SEMI ASMC, Infineon Technologies AG, pp. 17–20.
1 · Why raw cost-per-unit cannot be benchmarked
Leachman & Hodges found productivity indicators — yield, equipment production rate, wafer throughput time — vary by factors of 3 to 5 across comparable fabs in the US, Germany, Japan, Korea and Taiwan. Much of a fab's raw cost difference is its labour and energy prices, which say nothing about how well it is run.
2 · The reference route
For each product family we hold a reference bill of physical activity per wafer: direct-labour minutes, energy kWh, equipment euros and material euros. These quantities are the physics of the process; they do not depend on where the fab is.
Reference bill of activity per wafer (synthetic)
| Product family | Labour (min) | Energy (kWh) | Equipment (€) | Materials (€) |
|---|---|---|---|---|
| 3 nm (GAA, EUV) | 2,200 | 5,200 | 7,500 | 3,400 |
| 7 nm (EUV) | 1,850 | 4,200 | 4,700 | 2,600 |
| 28 nm (planar, DUV) | 1,000 | 1,900 | 1,100 | 540 |
| 130 nm (analog) | 450 | 500 | 430 | 260 |
| 180 nm (power) | 420 | 600 | 400 | 280 |
Source: Synthetic reference quantities, calibrated to published wafer-cost economics and fab energy intensity (≈1.2 kWh/cm²). Not measured values.
Reference process modules
Every wafer passes through these modules. Equipment cost = f(technology generation, plant age); depreciation runs off over the asset life (~7 years).
Public cost anchors
The synthetic reference quantities are calibrated to these public estimates. The synthetic 28 nm reference bill (≈ €2,451/wafer ≈ $2,700) lands right at the public ~$3,000 anchor.
Front end: wafer cost by node
| Node | Wafer (300 mm) | Mask set | Design / NRE |
|---|---|---|---|
| 28 nm | ~$3,000 | ~$2–3 M | $30–50 M |
| 7 nm | ~$9,500 | $10–15 M | $100–217 M |
| 5 nm | ~$18,500 | $15–25 M | $200–416 M |
| 3 nm | ~$19,500 | ~$40 M | $400–590 M |
Source: Wafer: TrendForce / Morgan Stanley (analyst estimates, Jul 2026); mask/NRE: IBS/Handel Jones; SemiAnalysis; CSET. Wafer +~6.5×, fixed cost (design + mask) +~15× across 28→3 nm.
Back end: packaging cost per unit
| Package technology | Cost / unit | Where |
|---|---|---|
| Wire bond | cents–$1 | QFN / BGA |
| Flip-chip (FCBGA) | $1–tens $ | mainstream logic |
| Fan-out (FOWLP) | $1–tens $ | mobile PoP → FOCoS |
| 2.5D (CoWoS) | $300–2,000 | HBM / AI · H100 ~$750 |
| 3D (SoIC/Foveros) | +$80–120 | stacking add-on |
Source: CoWoS cost/chip: Silicon Analysts / Morgan Stanley (Jul 2026) — H100 ~$750 (CoWoS-S), B200 ~$1,000–1,100 (CoWoS-L). AI-driven price hikes 2025–26: TSMC CoWoS +10–20%, ASE +20%. Yole/TechInsights. A 1% packaging/test defect cuts margin 5–7%.
3 · Standardization
We re-price that activity at one common set of reference factor prices — €35/h loaded labour and €0.12/kWh electricity — keeping the plant's own yield and equipment. What remains, standardized €/good wafer, is comparable across plants and geographies.
Reference labour
€35/h
Reference energy
€0.12/kWh
Equipment
f(generation, plant age)
4 · The normalization bridge
The gap between actual and standardized cost decomposes cleanly: a labour-context step, an energy-context step, and an equipment-vintage step. Each changes exactly one factor, so the euros attribute without overlap.
per wafer = labour·rate + energy·price + materials + ( equip/gen·age + overhead ) / OEE
€/good = per wafer / yield
cost bridge = reference plant → this fab, decomposed into six levers:
people · energy · equipment age · OEE · overheads · yield5 · Operational KPIs
Alongside cost we benchmark the canonical operational KPIs — line and die yield, defect density D₀, cycle time per mask layer, WIP turns, OEE and DPPM — with the correlations an expert expects (low D₀ ↔ high yield; high WIP turns ↔ low cycle time).
Wafer fab (front-end)
| KPI | Unit | Better when |
|---|---|---|
| Line yield Share of wafers that complete the line without being scrapped. Typically 95–99.5%. | % | higher |
| Die yield Share of good dies per wafer. Falls with defect density and die area. | % | higher |
| Defect density (D₀) Defects per cm². ~0.15 in mature processes, 0.3–0.5 in ramp. | defects/cm² | lower |
| Cycle time Manufacturing days per mask layer. Median ~1.2–1.8. | days/mask layer | lower |
| WIP turns Throughput over work-in-progress. Median ~3–5. | turns | higher |
| Equipment OEE Availability × Performance × Quality. Median ~65–75%. | % | higher |
| DPPM Defective parts per million shipped. <500 mature, 2000+ ramp. | ppm | lower |
| Indirect overhead Indirect overhead (facilities, indirect labour, SG&A allocation) per wafer, 100 = reference. A fab-level fixed cost absorbed over throughput. | index (100 = median) | lower |
| Cost per wafer (self-reported) Your own relative cost per wafer, 100 = reference median. Distinct from the standardized cost computed from your factor inputs. | index (100 = median) | lower |
Assembly & test (back-end)
| KPI | Unit | Better when |
|---|---|---|
| Assembly yield Share of dies packaged without failure. Typically 98–99.8%. | % | higher |
| Test yield Share of final units passing final test. Cannot exceed source die yield. | % | higher |
| UPH (per line) Units per hour per line, normalized by package type. | units/hour | higher |
| First Pass Yield Product of per-station yields. | % | higher |
| Burn-in reject rate Rejects at burn-in, in ppm. | ppm | lower |
| DPPM to customer Defective parts per million shipped to the customer. | ppm | lower |
| Package cost Relative package cost, normalized to 100 at the reference median. | index (100 = median) | lower |
Die-yield model
Die yield from defect density and die area via Murphy's limited-area yield model:
Y = [ (1 − e^(−A·D₀)) / (A·D₀) ]²Reproduces the anchors: at A = 1 cm², D₀ = 0.10 gives ≈ 90.6 %, D₀ = 0.15 ≈ 86 %, D₀ = 0.30 ≈ 74.6 %.
Sources
Plieninger, Müller, Ehm & Reczek (2001) — the Reference Fab
R. Plieninger, U. Müller, H. Ehm and W. Reczek, "Cost Reduction using Systematic Target Setting of the Reference Fab Methodology," 2001 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Infineon Technologies AG, pp. 17–20.
The methodology this demonstration is built on. The Reference Fab sets cost targets top-down across three levels: an ideal greenfield fab at best-in-class performance in every cost category; a site-specific target obtained by applying factor/adders for local conditions (factor costs, volume, technology complexity, outsourcing); and a catch-up plan tracked against budget. Cost is split into capital, material, personnel and overhead (~15 categories), each with an efficiency = factor input ÷ pieces out. Infineon's Memory Products Division cut production cost by more than 25% (25–50% efficiency gains) versus initial plans.
Leachman & Hodges (1996)
R. C. Leachman and D. A. Hodges, "Benchmarking Semiconductor Manufacturing," IEEE Transactions on Semiconductor Manufacturing, vol. 9, no. 2, pp. 158–169, May 1996.
The benchmarking premise itself: productivity indicators (yield, equipment rate, throughput time) vary by 3–5× across comparable fabs — so normalization is required before comparison.
https://people.eecs.berkeley.edu/~hodges/IRWpaper.pdf →
Leachman, Yield Modeling (Berkeley CSM)
R. C. Leachman, "Yield Modeling and Analysis," UC Berkeley Competitive Semiconductor Manufacturing Program course notes.
Die-yield vs defect-density relationship (negative-binomial / Murphy model): yield falls as D₀ × die-area rises.
https://fog.misty.com/perry/cod/references/yield_models.pdf →
Eurostat, industrial electricity prices (2024)
Eurostat, Electricity price statistics — non-household (industrial) consumers, 2024. Germany ≈ €0.20–0.23/kWh; EU average ≈ €0.19/kWh.
Real industrial electricity-price spread used to calibrate local energy context (e.g. Germany ≈ €0.20/kWh vs Asian sites ≈ €0.08–0.10/kWh).
https://ec.europa.eu/eurostat/statistics-explained/index.php?title=Electricity_price_statistics →
Fab energy-intensity studies
Published fab energy studies report ≈ 1.15–1.43 kWh per cm² of wafer processed (e.g. Hu & Chuah, "Power consumption of semiconductor fabs," Energy, Elsevier).
Order-of-magnitude check on synthetic per-wafer energy (≈1.2 kWh/cm² × wafer area, scaled by mask-layer count for advanced logic).
https://www.sciencedirect.com/science/article/abs/pii/S0360544203000082 →
SEMI E10 / E79
SEMI E10 (equipment reliability, availability & maintainability) and SEMI E79 (definition and measurement of Overall Equipment Efficiency, OEE). SEMI International Standards.
OEE definition (Availability × Performance × Quality) and equipment-state accounting.
IEEE IRDS (ex-ITRS)
IEEE International Roadmap for Devices and Systems (IRDS), successor to the ITRS — defect-density and yield-learning targets by node.
Mature-node defect-density targets (D₀ order ~0.1–0.2 defects/cm²).
https://irds.ieee.org/ →
SEMATECH benchmarks
SEMATECH manufacturing benchmarks — historical industry reference ranges for DPPM, WIP turns and cycle-time-per-layer.
Reference ranges for DPPM, WIP turns and cycle time per mask layer.
TrendForce / Morgan Stanley wafer pricing (2026)
TrendForce and Morgan Stanley analyst estimates of TSMC 300 mm wafer prices, re-verified July 2026: 28 nm ~$3,000; 7 nm ~$9,500; 5 nm ~$18,500; 3 nm ~$19,500 (list; large customers ~15–30% below).
Public per-wafer cost anchors by node used to calibrate the synthetic front-end reference bill (28 nm synthetic ≈ $2,700 lands at the ~$3,000 anchor).
https://www.tomshardware.com/tech-industry/tsmcs-wafer-pricing-now-usd18-000-for-a-3nm-wafer-increased-by-over-3x-in-10-years-analyst →
Advanced-packaging cost estimates (2026)
Silicon Analysts / Morgan Stanley advanced-packaging cost estimates, re-verified July 2026: CoWoS-S ~$300–800/chip (H100 ~$750), CoWoS-L ~$800–2,000/chip (B200 ~$1,000–1,100); 3D SoIC add-on ~$80–120/unit; KGD test ~$5–15/chiplet. AI-driven price hikes 2025–26: TSMC CoWoS +10–20%, ASE +20%.
Public per-unit packaging cost anchors by technology used to calibrate the synthetic back-end reference bill and the assembly package generations.
https://www.trendforce.com/news/2026/07/01/news-ase-reportedly-raises-advanced-packaging-quotes-by-more-than-20-in-latest-ai-driven-price-hike/ →
Honesty note: the peer set and per-wafer quantities are synthetic — generated, not measured — and only calibrated to the ranges in the sources above. No proprietary, customer or real-plant data is used.